Semiconductor wafers are used to manufacture semiconductor devices including bipolar and MOS transistors designed for high-voltage or power applications. According to a conventional manufacturing process, doping regions and isolation regions are all processed from one side of the semiconductor wafer. A typical example of a high-voltage MOS transistor is a laterally diffused MOS transistor (LDMOS) as shown in FIG. 1 the constitution of which is briefly described below.
Provided is a semiconductor substrate 90 disposed in a semiconductor wafer 9 which includes a well doping region 86 that forms the channel of the LDMOS transistor 81, a doping area 85 that forms a drift region. A gate electrode 88 is disposed on a gate oxide on the semiconductor substrate 90. Doping region 78 establishes the source and doping region 79 establishes the drain of the LDMOS transistor. One or more dielectric layers 91 are provided to establish pre- and intermetal dielectric layers on the surface 90a of the semiconductor substrate 90. The dielectric layers 91 embed one or more layers of metal wirings 89. The wirings contact the doping regions and the gate electrode to carry signals and/or current into and from the drain and source doping regions and carry control signals to the gate electrode. For example, the drain electrode is connected to wiring layer portion 885. The gate electrode is connected to wiring layer portion 888. The signals from both wiring layers are available adjacent the surface 90a of the wafer 9. A pad 96 provides a metal connection at the top surface of the dielectric 91 so that a signal or a high voltage output or a drain current is available to the outside of the device so that it can be connected to an external circuit. A passivation 92 covers the top side of the device except the pad areas.
Isolation regions surrounding the LDMOS transistor such as deep trench isolations 99 isolate the transistor from other devices and structures integrated within the wafer. The wafer may include other power devices or a CMOS circuit 80 that comprises a p-channel transistor and an n-channel transistor. The CMOS circuit can include well doping regions 83, source/drain doping regions 84 and gate electrodes including gate oxides 87. The CMOS transistors may be isolated by shallow trenches 82. The CMOS circuit is connected to the wiring layers 89 to receive and output signals that may be used to control the operation of the LDMOS device.
Such a high-voltage LDMOS transistor may be operated at about 0 V (Volt) for the source electrode and about 40 V to 100 V at the drain electrode so that transistors designed for high break down voltages may generate large depletion zones during operation that extend deep into the substrate. Such depletion zones may cause issues with parasitic capacitances and leakage currents that may degrade the performance of the transistor.
Conventional manufacturing processes employ a silicon on insulator (SOI) substrate that includes a buried insulation region 98 such as a buried oxide that isolates the active regions of the wafer from the other portions of the wafer beneath the buried oxide. The thickness of the substrate of the active area of the transistor becomes limited on a SOI substrate. However, the use of a silicon on insulator substrate is complex to manufacture and expensive in terms of costs. Furthermore, the low thermal conductivity of the buried oxide layer makes it difficult to remove heat form the high voltage transistor during operation. The fabrication of vertical high voltage transistors is difficult with a SOI substrate according to the conventional approach because access to the lower electrodes may be complicated and vertical high voltage transistors are difficult to integrate with lateral transistors.
It is therefore desirable to provide a process to manufacture high-voltage and/or power devices that is less complex, generates devices with predictable parameters and is less expensive.